This invention is applicable to data processing systems with second level (L2) memory used for both unified (code and instructions) level two cache and flat (L2 SRAM) memory used to hold critical data and instructions. Such a second level memory has multiple endpoints and use cases for the corresponding memory controller. This level two memory controller can access level two SRAM, level two cache and external memories. This memory controller receives access requests from different requestors including the central processing unit (CPU) for data and instructions, internal cache block operations and internal or slave direct memory access (DMA) units. These access requests can have multiple destinations including flat memory (L2 SRAM), level two cache and external endpoints. These access requests can be of four types including reads, writes, victims and allocates.
The number of permutations of transactions possible for requestor/endpoint pairs is large. All memory transfers require the highest bandwidth possible. These permutations of possible transactions can be divided into three major types. The first type of these permutations include different requestors to different endpoint destinations. These requests should not interfere with each other and their performance should not affect each other. The second type of these permutations include different requestors to the same endpoint. These transactions should see a change in performance only when there is an actual conflict in resources. The third type of these permutations include the same requestor to different endpoints. These transactions should be able to proceed in parallel with their only interaction being on the interface between the requestor and the controller. All types of accesses should be independent of external influences such as stalls from external endpoints.